//
// Title        : (74)D-FF with Preset and Clear Verilog-HDL file
// File name    : 74.v
// Date         : 2000/12/08  Ver1.0
// Company      : Future Technology Ltd.
//

//----------------------------------------------------
//  Module
//----------------------------------------------------

module U74(
            XCLR,
            XPR,
            CLK,
            D,
            Q
        );

    input           XCLR;
    input           XPR;
    input           CLK;
    input           D;
    output          Q;

//----------------------------------------------------
//  Using Register
//----------------------------------------------------
    reg             Q;


    always@( posedge CLK or negedge XCLR or negedge XPR)begin
        if(XCLR == 1'b0)begin
            Q   <= 1'b0;
        end else if(XPR == 1'b0)begin
            Q   <= 1'b1;
        end else begin
            Q   <= D;
        end
    end

endmodule