// 
// Title        ： (4040) 12-STAGE BINARY COUNTERS
// File name    ： 4040.v 
// Date         ： 2000/12/08 Ver1.0 
// Company      ： Future Technology Ltd. 
// 

//----------------------------------------------------
//  Module
//----------------------------------------------------

module U4040(
            CLK,
            CLR,
            QA,
            QB,
            QC,
            QD,
            QE,
            QF,
            QG,
            QH,
            QI,
            QJ,
            QK,
            QL
        );

    input           CLK;
    input           CLR;
    output          QA;
    output          QB;
    output          QC;
    output          QD;
    output          QE;
    output          QF;
    output          QG;
    output          QH;
    output          QI;
    output          QJ;
    output          QK;
    output          QL;

//----------------------------------------------------
//  Using Register
//----------------------------------------------------
    reg             QA;
    reg             QB;
    reg             QC;
    reg             QD;
    reg             QE;
    reg             QF;
    reg             QG;
    reg             QH;
    reg             QI;
    reg             QJ;
    reg             QK;
    reg             QL;


    always@(negedge CLK or posedge CLR)begin
        if(CLR==1'b1)begin
            QA <= 1'b0;
        end else begin
            QA <= ~QA;
        end
    end

    always@(negedge QA or posedge CLR)begin
        if(CLR==1'b1)begin
            QB <= 1'b0;
        end else begin
            QB <= ~QB;
        end
    end

    always@(negedge QB or posedge CLR)begin
        if(CLR==1'b1)begin
            QC <= 1'b0;
        end else begin
            QC <= ~QC;
        end
    end

    always@(negedge QC or posedge CLR)begin
        if(CLR==1'b1)begin
            QD <= 1'b0;
        end else begin
            QD <= ~QD;
        end
    end

    always@(negedge QD or posedge CLR)begin
        if(CLR==1'b1)begin
            QE <= 1'b0;
        end else begin
            QE <= ~QE;
        end
    end

    always@(negedge QE or posedge CLR)begin
        if(CLR==1'b1)begin
            QF <= 1'b0;
        end else begin
            QF <= ~QF;
        end
    end

    always@(negedge QF or posedge CLR)begin
        if(CLR==1'b1)begin
            QG <= 1'b0;
        end else begin
            QG <= ~QG;
        end
    end

    always@(negedge QG or posedge CLR)begin
        if(CLR==1'b1)begin
            QH <= 1'b0;
        end else begin
            QH <= ~QH;
        end
    end

    always@(negedge QH or posedge CLR)begin
        if(CLR==1'b1)begin
            QI <= 1'b0;
        end else begin
            QI <= ~QI;
        end
    end

    always@(negedge QI or posedge CLR)begin
        if(CLR==1'b1)begin
            QJ <= 1'b0;
        end else begin
            QJ <= ~QJ;
        end
    end

    always@(negedge QJ or posedge CLR)begin
        if(CLR==1'b1)begin
            QK <= 1'b0;
        end else begin
            QK <= ~QK;
        end
    end

    always@(negedge QK or posedge CLR)begin
        if(CLR==1'b1)begin
            QL <= 1'b0;
        end else begin
            QL <= ~QL;
        end
    end

endmodule