//
// Title        : (299) 8-BIT SHIFT REGISTER
// File name    : 299.v
// Date         : 2000/12/08  Ver1.0
// Company      : Future Technology Ltd.
//

//-----------------------------------------------------
//  Module
//-----------------------------------------------------

module U299(
            XCLR,
            S1,
            S0,
            XOE1,
            XOE2,
            CLK,
            SL,
            SR,
            AQA,
            BQB,
            CQC,
            DQD,
            EQE,
            FQF,
            GQG,
            HQH,
            QAO,
            QHO
        );

    input           XCLR;
    input           S1;
    input           S0;
    input           XOE1;
    input           XOE2;
    input           CLK;
    input           SL;
    input           SR;
    inout           AQA;
    inout           BQB;
    inout           CQC;
    inout           DQD;
    inout           EQE;
    inout           FQF;
    inout           GQG;
    inout           HQH;
    output          QAO;
    output          QHO;

//-----------------------------------------------------
//  Using register
//-----------------------------------------------------
    reg     sr_qa;
    reg     sr_qb;
    reg     sr_qc;
    reg     sr_qd;
    reg     sr_qe;
    reg     sr_qf;
    reg     sr_qg;
    reg     sr_qh;


    always@(posedge CLK or negedge XCLR)begin
        if(XCLR==1'b0)begin                          //クリア
            sr_qa   <= 1'b0;
            sr_qb   <= 1'b0;
            sr_qc   <= 1'b0;
            sr_qd   <= 1'b0;
            sr_qe   <= 1'b0;
            sr_qf   <= 1'b0;
            sr_qg   <= 1'b0;
            sr_qh   <= 1'b0;
        end else if(S1==1'b0 & S0==1'b1)begin       // 右シフト
            sr_qa   <= SR;
            sr_qb   <= sr_qa;
            sr_qc   <= sr_qb;
            sr_qd   <= sr_qc;
            sr_qe   <= sr_qd;
            sr_qf   <= sr_qe;
            sr_qg   <= sr_qf;
            sr_qh   <= sr_qg;
        end else if(S1==1'b1 & S0==1'b0)begin       // 左シフト
            sr_qa   <= sr_qb;
            sr_qb   <= sr_qc;
            sr_qc   <= sr_qd;
            sr_qd   <= sr_qe;
            sr_qe   <= sr_qf;
            sr_qf   <= sr_qg;
            sr_qg   <= sr_qh;
            sr_qh   <= SL;
        end else if(S1==1'b1 & S0==1'b1)begin       // ロード
            sr_qa   <= AQA;
            sr_qb   <= BQB;
            sr_qc   <= CQC;
            sr_qd   <= DQD;
            sr_qe   <= EQE;
            sr_qf   <= FQF;
            sr_qg   <= GQG;
            sr_qh   <= HQH;
        end
    end

//---XOE-----------------------------------------------
    assign  AQA = (XOE1==1'b0 && XOE2==1'b0 && 
                   !(S1==1'b1 && S0==1'b1))?sr_qa:Z;
    assign  BQB = (XOE1==1'b0 && XOE2==1'b0 && 
                   !(S1==1'b1 && S0==1'b1))?sr_qb:Z;
    assign  CQC = (XOE1==1'b0 && XOE2==1'b0 && 
                   !(S1==1'b1 && S0==1'b1))?sr_qc:Z;
    assign  DQD = (XOE1==1'b0 && XOE2==1'b0 && 
                   !(S1==1'b1 && S0==1'b1))?sr_qd:Z;
    assign  EQE = (XOE1==1'b0 && XOE2==1'b0 && 
                   !(S1==1'b1 && S0==1'b1))?sr_qe:Z;
    assign  FQF = (XOE1==1'b0 && XOE2==1'b0 && 
                   !(S1==1'b1 && S0==1'b1))?sr_qf:Z;
    assign  GQG = (XOE1==1'b0 && XOE2==1'b0 && 
                   !(S1==1'b1 && S0==1'b1))?sr_qg:Z;
    assign  HQH = (XOE1==1'b0 && XOE2==1'b0 && 
                   !(S1==1'b1 && S0==1'b1))?sr_qh:Z;

//---QAO-QHO-------------------------------------------
    assign  QAO = sr_qa;
    assign  QHO = sr_qh;

endmodule