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型式74xx191ICのVerilog-HDLモデルです。


//
// Title      : (191) SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
// File name  : 191.v
// Date       : 2000/12/08  Ver1.0
// Company    : Future Technology Ltd.
//

//-----------------------------------------------------
//  Module
//-----------------------------------------------------

module U191 (
            CLK,
            XCEG,
            DXU,
            XLOAD,
            D,
            MAXMIN,
            Q
        );

    input           CLK;
    input           XCEG;
    input           DXU;
    input           XLOAD;
    input   [3:0]   D;
    output          MAXMIN;
    output  [3:0]   Q;

//-----------------------------------------------------
//  Using register
//-----------------------------------------------------
    reg     [3:0]   Q;
//-----------------------------------------------------
//  Using wire
//-----------------------------------------------------
    wire            s_max;
    wire            s_min;


    always@(posedge CLK or negedge XLOAD or D)begin
        if(XLOAD==1'b0)begin                        // LOAD
            Q       <= D;
        end else if(DXU==1'b0 && XCEG==1'b0)begin   // Count Up
            Q       <= Q + 4'b0001;
        end else if(DXU==1'b1 && XCEG==1'b0)begin   // Count Down
            Q       <= Q - 4'b0001;
        end
    end

    assign s_max = (Q==4'b1111 && XCEG==1'b0 && DXU==1'b0);

    assign s_min = (Q==4'b0000 && XCEG==1'b0 && DXU==1'b1);

    assign MAXMIN = s_max | s_min;

endmodule



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