//
// Title        : (166)8-bit SHift Register(no use clock Inh)
// File name    : 166.v
// Date         : 2000/12/08  Ver1.0
// Company      : Future Technology Ltd.
//

//-----------------------------------------------------
//  Module
//-----------------------------------------------------

module U166(
            XCLR,
            CLK,
            SLD,
            SI,
            D,
            QH
        );

    input           XCLR;
    input           CLK;
    input           SLD;
    input           SI;
    input   [7:0]   D;
    output          QH;

//-----------------------------------------------------
//  Using Register
//-----------------------------------------------------
    reg     [7:0]   sr_d;


    always@(posedge CLK or negedge XCLR)begin
        if(XCLR==1'b0)begin
            sr_d    <= 8'b00000000;
        end else if(SLD==1'b0)begin
            sr_d    <= D;
        end else begin
            sr_d[7] <=  SI;
            sr_d[6] <=  sr_d[7];
            sr_d[5] <=  sr_d[6];
            sr_d[4] <=  sr_d[5];
            sr_d[3] <=  sr_d[4];
            sr_d[2] <=  sr_d[3];
            sr_d[1] <=  sr_d[2];
            sr_d[0] <=  sr_d[1];
        end
    end

    assign QH  = sr_d[0];

endmodule