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型式74xx147ICのVerilog-HDLモデルです。


//
// Title        : (147) 10 to 4 Priority Encoder
// File name    : 147.v
// Date         : 2000/12/08  Ver1.0
// Company      : Future Technology Ltd.
//

//----------------------------------------------------------
//  Module
//----------------------------------------------------------

module U147 (
            E,
            A,
            B,
            C,
            D
        );

    input   [9:1]   E;
    output          A;
    output          B;
    output          C;
    output          D;

//----------------------------------------------------------
//  Using register
//----------------------------------------------------------
    reg     [3:0]   s_q;


    assign  A = s_q[0];
    assign  B = s_q[1];
    assign  C = s_q[2];
    assign  D = s_q[3];

    always@(E)begin
        casex(E[9:1])
            9'b0xxxxxxxx    :   s_q = 4'b0110;
            9'b10xxxxxxx    :   s_q = 4'b0111;
            9'b110xxxxxx    :   s_q = 4'b1000;
            9'b1110xxxxx    :   s_q = 4'b1001;
            9'b11110xxxx    :   s_q = 4'b1010;
            9'b111110xxx    :   s_q = 4'b1011;
            9'b1111110xx    :   s_q = 4'b1100;
            9'b11111110x    :   s_q = 4'b1101;
            9'b111111110    :   s_q = 4'b1110;
            default         :   s_q = 4'b1111;
        endcase
    end

endmodule



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