--
-- Title : MAIN CONTROL VHDL file
-- File name : STPRCTL.vhd
-- Date : 1998/09/21 Ver1.0
-- Company : Future Technology Ltd.
--
--使用ライブラリの設定
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
--ユーザ・ライブラリの設定
use WORK.DEF.all;
--エンティティ リスト
entity STPRCTL is
port(N_RST :in std_logic; -- reset
SYSCK :in std_logic; -- system clock (16MHz)
RPDMA_EN :in std_logic; -- system clock (16MHz)
N_4410W :in std_logic; -- 4420h write command
PRMODE :in std_logic_vector(1 downto 0); -- strobe mode
PRHIST :in std_logic; -- histry mode
STB_OUT_CYC :in std_logic; -- strobe output cycle end
DMA_END :in std_logic; -- dma end
REAL_TR_END :in std_logic; -- real data output end
HIST_TR_END :in std_logic; -- hist_data output end
NEW_PRMODE :out std_logic_vector(1 downto 0); -- strobe mode
OLD_PRMODE :out std_logic_vector(1 downto 0); -- old strobe mode
DMA_INIT :out std_logic; -- dma init
DMA_ST :out std_logic; -- dma cycle start
REAL_TR_ST :out std_logic; -- real data trans start
HIST_TR_ST :out std_logic; -- hist data trans start
STB_ST_REAL :out std_logic; -- real mode strobe start
STB_ST_HIST :out std_logic; -- histry mode strobe start
DMA_ADR_INIT :out std_logic; -- ram address init
DMA_SEL :out std_logic; -- rem control select
HIST_WR_WE :out std_logic; -- ram write enable
HIST_WRADR_INIT :out std_logic; -- ram address init
HIST_WRADR_EN :out std_logic; -- ram address count enable
HIST_WR_SEL :out std_logic; -- rem control select
REAL_RDADR_INIT :out std_logic; -- ram address init
REAL_RDADR_EN :out std_logic; -- ram address count enable
REAL_RD_SEL :out std_logic; -- rem control select
HIST_CLR_WE :out std_logic; -- ram write enable
HIST_CLRADR_INIT :out std_logic; -- ram address init
HIST_CLRADR_EN :out std_logic; -- ram address count enable
HIST_CLR_SEL :out std_logic; -- rem control select
LATCH_START :out std_logic; -- serial data latch start
TRANS_CNT2 :out std_logic; -- trans counter = 2
TRANS_CNT1 :out std_logic; -- trans counter = 1
-- test pin
MINDMA :out std_logic
);
end STPRCTL;
architecture TPRCTL of STPRCTL is
-- signal list --
-- dma start signal
signal dma_reg1 :std_logic;
signal dma_reg2 :std_logic;
signal dma_start :std_logic;
-- main sequencer
signal minst_ramclr_st :std_logic;
signal minst_ramclr :std_logic;
signal minst_dminit :std_logic;
signal minst_dmast :std_logic;
signal minst_dma :std_logic;
signal minst_mdschk :std_logic;
signal minst_dttrst :std_logic;
-- local sequencer
signal lclst_realdttr_st :std_logic;
signal lclst_realdttr :std_logic;
signal lclst_reallatch_chk :std_logic;
signal lclst_reallatch :std_logic;
signal lclst_realstb_st :std_logic;
signal lclst_histdttr_st :std_logic;
signal lclst_histdttr :std_logic;
signal lclst_histlatch_chk :std_logic;
signal lclst_histlatch :std_logic;
signal lclst_histstb_st :std_logic;
signal lclst_histdtwr_st :std_logic;
signal lclst_histdtwr :std_logic;
signal lclst_trcntdwn :std_logic;
signal lclst_trcntchk :std_logic;
signal lclst_end :std_logic;
-- real to tmp
signal histdtwr_reg1 :std_logic;
signal histdtwr_reg2 :std_logic;
-- ram read/write control counter
signal ram_cnt :std_logic_vector(7 downto 0);
signal ram_cnt_en :std_logic;
signal ram_cnt_clr :std_logic;
signal ram_cnt_end :std_logic;
-- ram end state signal
signal ram_clr_end :std_logic;
signal hist_wr_end :std_logic;
-- trans counter
signal trans_cnt :std_logic_vector(1 downto 0);
signal trans_cnt0 :std_logic;
-- mode register set end (4420W)
signal n_modeset_clr :std_logic;
signal mode_set_reg :std_logic;
signal mode_set_reg1 :std_logic;
signal mode_set_reg2 :std_logic;
signal mode_set_end :std_logic;
-- old prmode register
signal new_prmode_reg :std_logic_vector(1 downto 0);
signal old_prmode_reg :std_logic_vector(1 downto 0);
begin
-------- main start signal --------
process(SYSCK,N_RST)begin
if(N_RST='0')then
dma_reg1 <= '0';
dma_reg2 <= '0';
elsif(SYSCK' event and SYSCK='1')then
dma_reg1 <= RPDMA_EN;
dma_reg2 <= dma_reg1;
end if;
end process;
dma_start <= dma_reg1 and not dma_reg2;
--------------------------------
-------- main sequencer --------
--------------------------------
-- メイン・シーケンサ
-- ワンホット・シーケンサ（Ｆ／Ｆ一つで１つのステートを表すシーケンサ）
process(SYSCK,N_RST)begin
if(N_RST='0')then
minst_ramclr_st <= '0';
minst_ramclr <= '0';
minst_dminit <= '0';
minst_dmast <= '0';
minst_dma <= '0';
minst_mdschk <= '0';
minst_dttrst <= '0';
elsif(SYSCK' event and SYSCK='1')then
-- st1: ram data clear start state
minst_ramclr_st <= dma_start;
-- st2: ram data clear end state
if(minst_ramclr_st='1')then
minst_ramclr <= '1';
elsif(minst_ramclr ='1' and ram_clr_end='1')then
minst_ramclr <= '0';
end if;
-- st3: counter clear state
minst_dminit <= (minst_ramclr and ram_clr_end) or lclst_end;
-- st4: dma cycle start state
minst_dmast <= minst_dminit and dma_reg1;
-- st5: dma cycle state
if(minst_dmast='1')then
minst_dma <= '1';
elsif(DMA_END='1')then
minst_dma <= '0';
end if;
-- st6: mode set check state
if(minst_dma='1' and DMA_END='1')then
minst_mdschk <= '1';
elsif(mode_set_end='1')then
minst_mdschk <= '0';
end if;
-- st7: data trans start state
minst_dttrst <= minst_mdschk and mode_set_end;
end if;
end process;
--------------------------------
-------- local sequencer -------
--------------------------------
-- サブ・シーケンサ
process(SYSCK,N_RST)begin
if(N_RST='0')then
lclst_realdttr_st <= '0';
lclst_realdttr <= '0';
lclst_reallatch_chk <= '0';
lclst_reallatch <= '0';
lclst_realstb_st <= '0';
lclst_histdttr_st <= '0';
lclst_histdttr <= '0';
lclst_histlatch_chk <= '0';
lclst_histlatch <= '0';
lclst_histstb_st <= '0';
lclst_histdtwr_st <= '0';
lclst_histdtwr <= '0';
lclst_trcntdwn <= '0';
lclst_trcntchk <='0';
lclst_end <= '0';
elsif(SYSCK' event and SYSCK='1')then
-- st1: real data trans start state
lclst_realdttr_st <= minst_dttrst
or (lclst_trcntchk and not trans_cnt0);
-- st2: real data trans state
if(lclst_realdttr_st='1')then
lclst_realdttr<='1';
elsif(REAL_TR_END='1')then
lclst_realdttr<='0';
end if;
-- st3: strobe output end check
if(lclst_realdttr='1' and REAL_TR_END='1')then
lclst_reallatch_chk <= '1';
elsif(lclst_reallatch_chk='1' and STB_OUT_CYC='0')then
lclst_reallatch_chk <='0';
end if;
-- st4: data latch output
lclst_reallatch <= lclst_reallatch_chk and not STB_OUT_CYC;
-- st5: real strobe 1-4 output start state
lclst_realstb_st <= lclst_reallatch;
-- st6: hist data trans start state
lclst_histdttr_st <= lclst_realstb_st and PRHIST;
-- st7: hist data trans end state
if(lclst_histdttr_st='1')then
lclst_histdttr <= '1';
elsif(HIST_TR_END='1')then
lclst_histdttr <= '0';
end if;
-- st8: strobe output end check
if(lclst_histdttr='1' and HIST_TR_END='1')then
lclst_histlatch_chk <= '1';
elsif(lclst_histlatch_chk='1' and STB_OUT_CYC='0')then
lclst_histlatch_chk <='0';
end if;
-- st9: data latch output
lclst_histlatch <= lclst_histlatch_chk and not STB_OUT_CYC;
-- st10: hist strobe 1-4 output start state
lclst_histstb_st <= lclst_histlatch;
-- st11: real ram to hist ram data write start state
lclst_histdtwr_st <= lclst_histstb_st;
-- st12: real ram to hist ram data write state
if(lclst_histdtwr_st='1')then
lclst_histdtwr <= '1';
elsif(hist_wr_end='1')then
lclst_histdtwr <= '0';
end if;
-- st13: trans count down state
lclst_trcntdwn <= (lclst_histdtwr and hist_wr_end)
or (lclst_realstb_st and not PRHIST);
-- st14: trans count check state
lclst_trcntchk <= lclst_trcntdwn;
-- st15: local sequencer end state
lclst_end <= lclst_trcntchk and trans_cnt0;
end if;
end process;
-- dma control
DMA_INIT <= minst_dminit;
DMA_ST <= minst_dmast;
-- real data trans control
REAL_TR_ST <= lclst_realdttr_st;
-- hist data trans control
HIST_TR_ST <= lclst_histdttr_st;
-- real strobe output control
STB_ST_REAL <= lclst_realstb_st;
-- hist strobe output control
STB_ST_HIST <= lclst_histstb_st;
-- histry ram clear control
HIST_CLR_WE <= minst_ramclr;
HIST_CLRADR_INIT <= minst_ramclr_st;
HIST_CLRADR_EN <= minst_ramclr;
HIST_CLR_SEL <= minst_ramclr;
-- dma ram write control
DMA_ADR_INIT <= minst_dminit;
DMA_SEL <= minst_dma;
-- real ram read control(real to hist)
REAL_RDADR_INIT <= lclst_histdtwr_st;
REAL_RDADR_EN <= lclst_histdtwr;
REAL_RD_SEL <= lclst_histdtwr;
-- hist write control(real to hist or real to hist)
HIST_WR_WE <= histdtwr_reg2;
HIST_WRADR_INIT <= lclst_histdtwr_st;
HIST_WRADR_EN <= histdtwr_reg2;
HIST_WR_SEL <= histdtwr_reg2;
process(SYSCK,N_RST)begin
if(N_RST='0')then
histdtwr_reg1 <= '0';
histdtwr_reg2 <= '0';
elsif(SYSCK' event and SYSCK='1')then
histdtwr_reg1 <= lclst_histdtwr;
histdtwr_reg2 <= histdtwr_reg1;
end if;
end process;
-- serial data latch start
LATCH_START <= lclst_reallatch or lclst_histlatch;
-- Update : 1998/12/01 Ver1.2 : K.Bettou
-- mode register set end (4420W)
n_modeset_clr <= not (not N_RST or minst_dttrst or DMA_END);
-- Update : 1998/12/21 Ver1.3 : K.Bettou
process(n_4410w,n_modeset_clr)begin
if(n_modeset_clr='0')then
mode_set_reg <= '0';
elsif(n_4410w' event and n_4410w='1')then
mode_set_reg <= '1';
end if;
end process;
process(SYSCK,N_RST)begin
if(N_RST='0')then
mode_set_reg1 <= '0';
mode_set_reg2 <= '0';
elsif(SYSCK' event and SYSCK='1')then
mode_set_reg1 <= mode_set_reg;
mode_set_reg2 <= mode_set_reg1;
end if;
end process;
mode_set_end <= mode_set_reg1 and not mode_set_reg2;
-- ram read/write control counter
ram_cnt_clr <= minst_ramclr_st or lclst_histdtwr_st;
ram_cnt_en <= minst_ramclr or lclst_histdtwr;
process(SYSCK,N_RST)begin
if(N_RST='0')then
ram_cnt <= b"00000000";
elsif(SYSCK' event and SYSCK='1')then
if(ram_cnt_clr='1')then
ram_cnt <= b"00000000";
elsif(ram_cnt_en='1')then
ram_cnt <= ram_cnt + b"00000001";
end if;
end if;
end process;
ram_cnt_end <= '1' when (ram_cnt=WORD_COUNT_MAX) else '0';
ram_clr_end <= minst_ramclr and ram_cnt_end;
hist_wr_end <= lclst_histdtwr and ram_cnt_end;
-- trans counter
-- Update : 1998/11/27 Ver1.1 : K.Bettou
process(SYSCK,N_RST)begin
if(N_RST='0')then
trans_cnt <= b"00";
elsif(SYSCK' event and SYSCK='1')then
if(new_prmode_reg=b"11" and minst_dttrst='1')then
trans_cnt <= b"10";
elsif(new_prmode_reg/=b"11" and minst_dttrst='1')then
trans_cnt <= b"01";
elsif(lclst_trcntdwn='1')then
trans_cnt <= trans_cnt - b"01";
end if;
end if;
end process;
TRANS_CNT2 <= trans_cnt(1) and not trans_cnt(0);
TRANS_CNT1 <= not trans_cnt(1) and trans_cnt(0);
trans_cnt0 <= not trans_cnt(1) and not trans_cnt(0);
-- new prmode register
process(SYSCK,N_RST)begin
if(N_RST='0')then
new_prmode_reg <= b"00";
elsif(SYSCK' event and SYSCK='1')then
if(mode_set_end='1')then
new_prmode_reg <= PRMODE;
end if;
end if;
end process;
NEW_PRMODE <= new_prmode_reg;
-- old prmode register
process(SYSCK,N_RST)begin
if(N_RST='0')then
old_prmode_reg <= b"00";
elsif(SYSCK' event and SYSCK='1')then
if(lclst_trcntchk='1')then
old_prmode_reg <= new_prmode_reg;
end if;
end if;
end process;
OLD_PRMODE <= old_prmode_reg;
--------------------------------
-------- test pin -------
--------------------------------
MINDMA <= minst_dma;
end TPRCTL;
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