--
-- Title     : (83)4-bit Binary Adder
-- File name : 83.vhd
-- Date      : 2000/12/08  Ver1.0
-- Company   : Future Technology Ltd.
--

-- use library
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

-- entity list --
entity U83 is
    port (
        A   :   in  std_logic_vector(3 downto 0);
        B   :   in  std_logic_vector(3 downto 0);
        CI  :   in  std_logic;
        O   :   out std_logic_vector(3 downto 0);
        CO  :   out std_logic
      );
end U83;

-- architecture
architecture U83 of U83 is

-- signal list
signal  s_a     :   std_logic_vector(4 downto 0);
signal  s_b     :   std_logic_vector(4 downto 0);
signal  s_cin   :   std_logic_vector(4 downto 0);
signal  s_ans   :   std_logic_vector(4 downto 0);


begin

    s_a     <=  '0' & A;        --5'b
    s_b     <=  '0' & B;        --5'b
    s_cin   <=  "0000" & CI;    --5'b

    s_ans   <=  s_a + s_b + s_cin;

    O   <=  s_ans(3 downto 0);
    CO  <=  s_ans(4);

end U83;