--
-- Title     : (74)D-FF with Preset and Clear VHDL file
-- File name : 74.vhd
-- Date      : 2000/12/08  Ver1.0
-- Company   : Future Technology Ltd.
--

--  use library
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

--  entity list
entity U74 is
    port(
        XCLR    :   in  std_logic;
        XPR     :   in  std_logic;
        CLK     :   in  std_logic;
        D       :   in  std_logic;
        Q       :   out std_logic
      );
end U74;

--  architecture
architecture U74 of U74 is


begin

    process(CLK, XCLR, XPR)begin
        if(XCLR='0')then
            Q <= '0';
        elsif(XPR='0')then
            Q <= '1';
        elsif(CLK'event and CLK='1')then
            Q <= D;
        end if;
    end process;

end U74;