--
-- Title     : (42) BCD to Decimal Decoder VHDL file
-- File name : 42.vhd
-- Date      : 2000/12/08  Ver1.0
-- Company   : Future Technology Ltd.
--

--use library
library IEEE; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

--  entity library --
entity U42 is
    port(
        BCD : in    std_logic_vector(3 downto 0);
        O   : out   std_logic_vector(9 downto 0)
        );
end U42;

-- architecture --
architecture U42 of U42 is


begin

    process(BCD)begin
        case BCD is
            when    "0000"  =>  O   <= "1111111110";
            when    "0001"  =>  O   <= "1111111101";
            when    "0010"  =>  O   <= "1111111011";
            when    "0011"  =>  O   <= "1111110111";
            when    "0100"  =>  O   <= "1111101111";
            when    "0101"  =>  O   <= "1111011111";
            when    "0110"  =>  O   <= "1110111111";
            when    "0111"  =>  O   <= "1101111111";
            when    "1000"  =>  O   <= "1011111111";
            when    "1001"  =>  O   <= "0111111111";
            when    others  =>  O   <= "1111111111";
        end case;
    end process;

end U42;