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型式74xx373ICのVHDLモデルです。


--
-- Title     : (373) OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
-- File name : 373.vhd
-- Date      : 2000-12-08  Ver1.0
-- Company   : Future Technology Ltd.
--

-- use library --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

-- entity list --
entity U373 is
    port (
        XOC :   in  std_logic;
        C   :   in  std_logic;
        D   :   in  std_logic_vector(7 downto 0);
        Q   :   out std_logic_vector(7 downto 0)
      );
end U373;

-- architecture --
architecture U373 of U373 is

-- signal list --
signal  sr_q    : std_logic_vector(7 downto 0);


begin

    Q <= (others=>'Z') when (XOC='1') else sr_q;

    process(C,D)begin
        if(C='1')then
            sr_q <= D;
        end if;
    end process;

end U373;



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