--
-- Title        : (299) 8-BIT SHIFT REGISTER
-- File name    : 299.vhd
-- Date         : 2000-12-08  Ver1.0
-- Company      : Future Technology Ltd.
--

-- use library --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

-- entity list --
entity U299 is
    port (
        XCLR    : in    std_logic;
        S1      : in    std_logic;
        S0      : in    std_logic;
        XOE1    : in    std_logic;
        XOE2    : in    std_logic;
        CLK     : in    std_logic;
        SL      : in    std_logic;
        SR      : in    std_logic;
        AQA     : inout std_logic;
        BQB     : inout std_logic;
        CQC     : inout std_logic;
        DQD     : inout std_logic;
        EQE     : inout std_logic;
        FQF     : inout std_logic;
        GQG     : inout std_logic;
        HQH     : inout std_logic;
        QAO     : out   std_logic;
        QHO     : out   std_logic
      );
end U299;

-- architecture --
architecture U299 of U299 is

-- signal list --
signal  sr_qa   : std_logic;
signal  sr_qb   : std_logic;
signal  sr_qc   : std_logic;
signal  sr_qd   : std_logic;
signal  sr_qe   : std_logic;
signal  sr_qf   : std_logic;
signal  sr_qg   : std_logic;
signal  sr_qh   : std_logic;


begin

    process(CLK,XCLR)begin
        if(XCLR='0')then                    --クリア
            sr_qa   <= '0';
            sr_qb   <= '0';
            sr_qc   <= '0';
            sr_qd   <= '0';
            sr_qe   <= '0';
            sr_qf   <= '0';
            sr_qg   <= '0';
            sr_qh   <= '0';
        elsif(S1='0' and S0='1')then        -- 右シフト
            sr_qa   <= SR;
            sr_qb   <= sr_qa;
            sr_qc   <= sr_qb;
            sr_qd   <= sr_qc;
            sr_qe   <= sr_qd;
            sr_qf   <= sr_qe;
            sr_qg   <= sr_qf;
            sr_qh   <= sr_qg;
        elsif(S1='1' and S0='0')then        -- 左シフト
            sr_qa   <= sr_qb;
            sr_qb   <= sr_qc;
            sr_qc   <= sr_qd;
            sr_qd   <= sr_qe;
            sr_qe   <= sr_qf;
            sr_qf   <= sr_qg;
            sr_qg   <= sr_qh;
            sr_qh   <= SL;
        elsif(S1='1' and S0='1')then        -- ロード
            sr_qa   <= AQA;
            sr_qb   <= BQB;
            sr_qc   <= CQC;
            sr_qd   <= DQD;
            sr_qe   <= EQE;
            sr_qf   <= FQF;
            sr_qg   <= GQG;
            sr_qh   <= HQH;
        end if;
    end process;

-----XOE-----------------------------------------------
    AQA <= sr_qa when (XOE1='0' and XOE2='0' 
            and not(S1='1' and S0='1')) else 'Z';
    BQB <= sr_qb when (XOE1='0' and XOE2='0' 
            and not(S1='1' and S0='1')) else 'Z';
    CQC <= sr_qc when (XOE1='0' and XOE2='0' 
            and not(S1='1' and S0='1')) else 'Z';
    DQD <= sr_qd when (XOE1='0' and XOE2='0' 
            and not(S1='1' and S0='1')) else 'Z';
    EQE <= sr_qe when (XOE1='0' and XOE2='0' 
            and not(S1='1' and S0='1')) else 'Z';
    FQF <= sr_qf when (XOE1='0' and XOE2='0' 
            and not(S1='1' and S0='1')) else 'Z';
    GQG <= sr_qg when (XOE1='0' and XOE2='0' 
            and not(S1='1' and S0='1')) else 'Z';
    HQH <= sr_qh when (XOE1='0' and XOE2='0' 
            and not(S1='1' and S0='1')) else 'Z';

-----QAO-QHO-------------------------------------------
    QAO <= sr_qa;
    QHO <= sr_qh;

end U299;