--
-- Title        : (280) 9-Bit Parity Generators-Checkers
-- File name    : 280.vhd
-- Date         : 2000-12-08  Ver1.0
-- Company      : Future Technology Ltd.
--

-- use library --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

-- entity list --
entity U280 is
    port (
        A    :  in  std_logic;
        B    :  in  std_logic;
        C    :  in  std_logic;
        D    :  in  std_logic;
        E    :  in  std_logic;
        F    :  in  std_logic;
        G    :  in  std_logic;
        H    :  in  std_logic;
        I    :  in  std_logic;
        EVEN :  out std_logic;
        ODD  :  out std_logic
      );
end U280;

-- architecture --
architecture U280 of U280 is

-- signal list --
signal  s_odd : std_logic;


begin

    s_odd <= A xor B xor C xor D xor
             E xor F xor G xor H xor I;

    ODD <= s_odd;
    EVEN <= not s_odd;

end U280;