--
-- Title     : (191) SYNCHRONOUS 4-BIT UP-DOWN DECADE AND BINARY COUNTERS
-- File name : 191.vhd
-- Date      : 2000-12-08  Ver1.0
-- Company   : Future Technology Ltd.
--

-- use library --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

-- entity list --
entity U191 is
    port (
        CLK     : in    std_logic;
        XCEG    : in    std_logic;
        DXU     : in    std_logic;
        XLOAD   : in    std_logic;
        D       : in    std_logic_vector(3 downto 0);
        MAXMIN  : out   std_logic;
        Q       : out   std_logic_vector(3 downto 0)
      );
end U191;

-- architecture --
architecture U191 of U191 is

-- signal list --
signal  sr_q    : std_logic_vector(3 downto 0);
signal  s_max   : std_logic;
signal  s_min   : std_logic;


begin

    process(CLK,XLOAD,D)begin
        if(XLOAD='0')then                       -- LOAD
            sr_q        <= D;
        elsif(CLK' event and CLK='1')then
            if(DXU='0' and XCEG='0')then    -- Count Up
                sr_q        <= sr_q + "0001";
            elsif(DXU='1' and XCEG='0')then -- Count Down
                sr_q        <= sr_q - "0001";
            end if;
        end if;
    end process;

    s_max <= '1' when (sr_q="1111" and XCEG='0' and DXU='0') else '0';
    s_min <= '1' when (sr_q="0000" and XCEG='0' and DXU='1') else '0';
    MAXMIN <= s_max or s_min;

    Q <= sr_q;

end U191;