--
-- Title     : (166)8-bit SHift Register(no use clock Inh)
-- File name : 166.vhd
-- Date      : 2000/12/08  Ver1.0
-- Company   : Future Technology Ltd.
--

-- use library --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

-- entity list --
entity U166 is
    port (
        XCLR    : in    std_logic;
        CLK     : in    std_logic;
        SLD     : in    std_logic;
        SI      : in    std_logic;
        D       : in    std_logic_vector(7 downto 0);
        QH      : out   std_logic
      );
end U166;

-- architecture --
architecture U166 of U166 is

-- signal list --
signal sr_d : std_logic_vector(7 downto 0);


begin

    process(CLK,XCLR)begin
        if(XCLR='0')then
            sr_d    <= (others => '0');
        elsif(CLK' event and CLK='1')then
            if(SLD='0')then
                sr_d    <= D;
            else
                sr_d(7) <=  SI;
                sr_d(6) <=  sr_d(7);
                sr_d(5) <=  sr_d(6);
                sr_d(4) <=  sr_d(5);
                sr_d(3) <=  sr_d(4);
                sr_d(2) <=  sr_d(3);
                sr_d(1) <=  sr_d(2);
                sr_d(0) <=  sr_d(1);
            end if;
        end if;
    end process;

    QH  <= sr_d(0);

end U166;