--
-- Title      : (164) 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
-- File name  : 164.vhd
-- Date       : 2000-12-08  Ver1.0
-- Company    : Future Technology Ltd.
--

-- use library --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

-- entity list --
entity U164 is
    port (
        XCLR    : in    std_logic;
        CLK     : in    std_logic;
        A       : in    std_logic;
        B       : in    std_logic;
        QA      : out   std_logic;
        QB      : out   std_logic;
        QC      : out   std_logic;
        QD      : out   std_logic;
        QE      : out   std_logic;
        QF      : out   std_logic;
        QG      : out   std_logic;
        QH      : out   std_logic
      );
end U164;

-- architecture --
architecture U164 of U164 is

-- signal list --
signal  sr_qa   : std_logic;
signal  sr_qb   : std_logic;
signal  sr_qc   : std_logic;
signal  sr_qd   : std_logic;
signal  sr_qe   : std_logic;
signal  sr_qf   : std_logic;
signal  sr_qg   : std_logic;


begin

    process(XCLR,CLK)begin
        if(XCLR='0')then
            sr_qa   <= '0';
            sr_qb   <= '0';
            sr_qc   <= '0';
            sr_qd   <= '0';
            sr_qe   <= '0';
            sr_qf   <= '0';
            sr_qg   <= '0';
            QH      <= '0';
        elsif(CLK' event and CLK='1')then
            sr_qa   <= A and B;
            sr_qb   <= sr_qa;
            sr_qc   <= sr_qb;
            sr_qd   <= sr_qc;
            sr_qe   <= sr_qd;
            sr_qf   <= sr_qe;
            sr_qg   <= sr_qf;
            QH      <= sr_qg;
        end if;
    end process;

    QA <= sr_qa;
    QB <= sr_qb;
    QC <= sr_qc;
    QD <= sr_qd;
    QE <= sr_qe;
    QF <= sr_qf;
    QG <= sr_qg;

end U164;