-- 
-- Title      ： (163)Synchronous Presettable Binary Counter with Clear 
-- File name  ： 163.vhd 
-- Date       ： 2000/12/08 Ver1.0 
-- Company    ： Future Technology Ltd. 
-- 

-- use library --
library IEEE;
use IEEE.   std_logic_1164.all;
use IEEE.   std_logic_unsigned.all;
use IEEE.   std_logic_arith.all;

-- entity list --
entity U163 is
    port (
        XCLR    : in    std_logic;
        CLK     : in    std_logic;
        LD      : in    std_logic;
        D       : in    std_logic_vector(3 downto 0);
        ENP     : in    std_logic;
        ENT     : in    std_logic;
        Q       : out   std_logic_vector(3 downto 0);
        RI      : out   std_logic
      );
end U163;

-- architecture --
architecture U163 of U163 is

-- signal list --
signal  s_en    : std_logic;
signal  s_ri    : std_logic;
signal  sr_cnt  : std_logic_vector(3 downto 0); 


begin

    s_en    <=  ENP and ENT;

    process(CLK)begin
        if(CLK' event and CLK='1')then
            if(XCLR='0')then                --クリア
                sr_cnt <= (others => '0');
            elsif(LD='0')then               --ロード
                sr_cnt <= D;
            elsif(s_en='1')then
                sr_cnt <= sr_cnt + "0001";
            end if;
        end if;
    end process;

    s_ri <= '1' when (sr_cnt="1111") else '0';
    RI   <= s_ri and ENT;

    Q    <= sr_cnt;

end U163;