--
-- Title        : (147) 10 to 4 Priority Encoder
-- File name    : 147.vhd
-- Date         : 2000-12-08  Ver1.0
-- Company      : Future Technology Ltd.
--

-- use library --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

-- entity list --
entity U147 is
    port(
        E   :   in  std_logic_vector(8 downto 0);
        A   :   out std_logic;
        B   :   out std_logic;
        C   :   out std_logic;
        D   :   out std_logic
      );
end U147;

-- architecture --
architecture U147 of U147 is

-- signal list --
signal  s_q  :  std_logic_vector(3 downto 0);


begin

    A <= s_q(0);
    B <= s_q(1);
    C <= s_q(2);
    D <= s_q(3);

    process(E)begin
        if(E(8)='0')then
            s_q <= "0110";
        elsif(E(7)='0')then
            s_q <= "0111";
        elsif(E(6)='0')then
            s_q <= "1000";
        elsif(E(5)='0')then
            s_q <= "1001";
        elsif(E(4)='0')then
            s_q <= "1010";
        elsif(E(3)='0')then
            s_q <= "1011";
        elsif(E(2)='0')then
            s_q <= "1100";
        elsif(E(1)='0')then
            s_q <= "1101";
        elsif(E(0)='0')then
            s_q <= "1110";
        else
            s_q <= "1111";
        end if;
    end process;

end U147;