--
-- Title     : (138) 3 to 8 Demultiplexer
-- File name : 138.vhd
-- Date      : 2000/12/08  Ver1.0
-- Company   : Future Technology Ltd.
--

-- use library --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

-- entity list
entity U138 is
    port(
        G1      : in    std_logic;
        XG2A    : in    std_logic;
        XG2B    : in    std_logic;
        I       : in    std_logic_vector(2 downto 0);
        Y       : out   std_logic_vector(7 downto 0)
      );
end U138;

-- architecture --
architecture U138 of U138 is

-- signal list --
signal  s_in    :   std_logic_vector(5 downto 0);


begin

   s_in    <= G1 & XG2A & XG2B & I;

    process(s_in)begin
        case s_in is
            when    "100000"    =>  Y   <= "11111110";
            when    "100001"    =>  Y   <= "11111101";
            when    "100010"    =>  Y   <= "11111011";
            when    "100011"    =>  Y   <= "11110111";
            when    "100100"    =>  Y   <= "11101111";
            when    "100101"    =>  Y   <= "11011111";
            when    "100110"    =>  Y   <= "10111111";
            when    "100111"    =>  Y   <= "01111111";
            when    others      =>  Y   <= "11111111";
        end case;
    end process;


end U138;