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型式74xx109ICのVHDLモデルです。


--
-- Title     : (109)JK-FF with Preset and Clear
-- File name : 109.vhd
-- Date      : 2000/12/08  Ver1.0
-- Company   : Future Technology Ltd.
--

--  use library --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

--  entity list --
entity U109 is
    port (
        XCLR    : in    std_logic;
        XPR     : in    std_logic;
        CLK     : in    std_logic;
        J       : in    std_logic;
        K       : in    std_logic;
        Q       : out   std_logic
      );
end U109;

-- architecture --
architecture U109 of U109 is

-- signal list --
signal  sr_q    : std_logic;


begin

    process(CLK,XCLR,XPR)begin
        if(XCLR='0')then
            sr_q    <= '0';
        elsif(XPR='0')then
            sr_q    <= '1';
        elsif(CLK' event and CLK='1')then
            if(J='1' and K='0')then
                sr_q    <= '1';
            elsif(J='0' and K='1')then
                sr_q    <= '0';
            elsif(J='1' and K='1')then
                sr_q    <= not sr_q;
           end if;
        end if;
    end process;

    Q <= sr_q;

end U109;



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